The present technique relates to the field of integrated circuits. More particularly, the technique relates to static timing analysis.
Static timing analysis (STA) is a method for determining expected timings of signal paths in an integrated circuit design. This is useful for checking whether the integrated circuit will operate correctly when manufactured. Typically, STA uses a representation of the integrated circuit design that identifies various logic cells of the circuit and specifies how they are connected together. Based on the properties of each logic cell, the delay through timing paths of the circuit can be estimated to determine whether the design would cause any timing violations which could lead to incorrect behaviour. If necessary, the integrated circuit design can then be modified to eliminate the timing violations which were detected.
In practice, the actual propagation delay through a logic cell may vary from chip to chip, between different areas of a chip, or with time, for example due to process, voltage and temperature variations. Therefore, a single value for the expected delay through a cell may not be enough, and so the static timing analysis may use a timing derate to characterise the variation in the delay through the cell. The timing derate allows the STA tool to estimate likely minimum or maximum delays and hence determine whether an integrated circuit design is likely to meet its timing requirements across a range of corner conditions. The present technique seeks to provide an improved method of using timing derates.